Semiconductor device and method for fabricating the same

ABSTRACT

Described is a method for fabricating a semiconductor device having an FET of a trench-gate structure obtained by disposing a conductive layer, which will be a gate, in a trench extended in the main surface of a semiconductor substrate, wherein the upper surface of the trench-gate conductive layer is formed equal to or higher than the main surface of the semiconductor substrate. In addition, the conductive layer of the trench gate is formed to have a substantially flat or concave upper surface and the upper surface is formed equal to or higher than the main surface of the semiconductor substrate. Moreover, after etching of the semiconductor substrate to form the upper surface of the conductive layer of the trench gate equal to or higher than the main surface of the semiconductor substrate, a channel region and a source region are formed by ion implantation. The semiconductor device thus fabricated according to the present invention is free from occurrence of a source offset.

BACKGROUND OF THE INVENTION

[0001] This invention relates to a semiconductor device, particularly, atechnique effective when adapted to a semiconductor device having atrench-gate structure.

[0002] A power transistor has been used for various applicationsincluding a power amplifier circuit, power supply circuit, converter andpower supply protective circuit. Since it treats high power, it isrequired to have high breakdown voltage and to permit high current.

[0003] In the case of MISFET (Metal Insulator Semiconductor Field EffectTransistor), high current can be attained easily by an expansion of achannel width. In order to avoid an increase in a chip area caused byexpansion of a channel width, a mesh-gate structure is, for example,employed.

[0004] Gates are two-dimensionally arranged in the form of a lattice inthe mesh-gate structure so that a channel width per unit chip area canbe enlarged. A description of an FET having a mesh-gate structure can befound on pages 429 to 430 of “Semiconductor Handbook” published byOhmsha Limited or U.S. Pat. No. 5,940,721.

[0005] For such a power FET, a planar structure has conventionally beenemployed because its fabrication process is simple and an oxide filmwhich will be a gate insulating film can be formed easily. In theabove-described U.S. Pat. No. 5,940,721 shown is an FET having a planarstructure.

[0006] The FET having a planar structure is however accompanied with thedrawbacks that when a gate is formed narrowly, the channel lengthbecomes short and a short-channel effect appears because the channellength is determined depending on the gate length; or when a gate isformed narrowly, an allowable current decreases because the gate hasadditionally a function of wiring. It is therefore impossible to conductminiaturization freely. With the foregoing in view, adoption of an FEThaving a trench-gate structure is considered because it can improve theintegration degree of cells and in addition, reduce an on resistance.

[0007] The trench-gate structure is formed by disposing, via aninsulating film, a conductive layer, which will serve as a gate, in atrench extended in the main surface of a semiconductor substrate and inthis structure, the deeper portion and the outer surface portion of themain surface serve as a drain region and a source region, respectivelyand a semiconductor layer between the drain and source regions serves asa channel forming region. Such a structure is described, for example, inU.S. Pat. No. 5,918,114.

[0008] The present inventors developed a technique for introducingimpurities into a source region or channel forming region of an MISFEThaving a trench-gate structure after the formation of a trench gate witha view to preventing a deterioration of a gate insulating film or afluctuation in a threshold voltage owing to the impurities in the sourceregion or channel forming region and have already applied for a patentas U.S. patent application Ser. No. 09/137,508.

SUMMARY OF THE INVENTION

[0009] With an advance of the miniaturization of a device, there is atendency to make the source region shallower. When the source regionbecomes shallower, however, it becomes difficult to place a trench gateat a precise position and the end portion of the trench gate does notoverlap with the source region. If a source offset occurs, in otherwords, the trench gate gets out of the source region, by inaccuratepositioning of the trench gate, this source offset impairs thefunctioning of the FET.

[0010] An object of the present invention is to provide a techniquecapable of overcoming the above-described problem and preventing theoccurrence of a source offset.

[0011] The above-described and the other objects and novel features ofthe present invention will be apparent from the description herein andaccompanying drawings.

[0012] Among the inventions disclosed by the present application,representative ones will next be summarized simply.

[0013] Provided is a semiconductor device equipped with an FET of atrench-gate structure having a conductive layer, which will be a gate,disposed in a trench extended in the main surface of a semiconductorsubstrate, wherein the upper surface of the trench-gate conductive layeror gate electrode is formed equal to or higher than the main surface ofthe semiconductor substrate.

[0014] Also provided is a semiconductor device equipped with an FET of atrench-gate structure having a conductive layer, which will be a gate,disposed in a trench extended in the main surface of a semiconductorsubstrate, wherein the trench-gate conductive layer (gate electrode) hasa substantially flat or convex upper surface and this upper surface ofthe trench-gate conductive layer is formed equal to or higher than themain surface of the semiconductor substrate.

[0015] Also provided is a semiconductor device equipped with an FET of atrench-gate structure having a conductive layer, which will be a gate,disposed in a trench extended in the main surface of a semiconductorsubstrate, wherein the upper surface of the trench-gate conductive layeris formed equal to or higher than the main surface of the semiconductorsubstrate and the trench gate has, at the terminal portion thereof, afield relaxing portion disposed.

[0016] Also provided is a fabrication method of a semiconductor deviceequipped with an FET of a trench-gate structure having a conductivelayer, which will be a gate, disposed in a trench extended in the mainsurface of a semiconductor substrate, which comprises:

[0017] forming a trench, wherein a trench-gate will be formed, in themain surface of the semiconductor substrate;

[0018] forming a gate insulating film in the trench,

[0019] forming a trench gate in the trench,

[0020] forming an-insulating film over the main surface of thesemiconductor substrate by thermal oxidation so that the film on thetrench gate becomes thicker than that on the main surface of thesemiconductor substrate by making use of the accelerated oxidationphenomenon,

[0021] removing the insulating film by etching and while leaving thethickly formed insulating film on the trench gate, exposing the mainsurface of the semiconductor substrate, and

[0022] selectively removing the semiconductor substrate relative to theinsulating film by etching, thereby forming the upper surface of thetrench gate covered with the insulating film equal to or higher than themain surface of the semiconductor substrate.

[0023] Also provided is a fabrication method of a semiconductor deviceequipped with an FET of a trench-gate structure having a conductivelayer, which will be a gate, disposed in a trench extended in the mainsurface of a semiconductor substrate, which comprises:

[0024] forming a trench, wherein a trench-gate will be formed, on themain surface of the semiconductor substrate;

[0025] forming a gate insulating film in the trench,

[0026] forming a trench gate in the trench,

[0027] forming an insulating film over the main surface of thesemiconductor substrate by thermal oxidation so that the film on thetrench gate becomes thicker than that on the main surface of thesemiconductor substrate by making use of the accelerated oxidationphenomenon,

[0028] removing the insulating film by etching and while leaving thethickly formed insulating film on the trench gate, exposing the mainsurface of the semiconductor substrate,

[0029] selectively removing the semiconductor substrate relative to theinsulating film by etching, thereby forming the upper surface of thetrench gate covered with the insulating film equal to or higher than themain surface of the semiconductor substrate, and

[0030] subsequent to the selective etching, introducing impurities fromthe main surface of the semiconductor substrate, thereby forming achannel forming region and a source region.

[0031] Also provided is a fabrication method of a semiconductor deviceequipped with an FET of a trench-gate structure having a conductivelayer, which will be a gate, disposed in a trench extended in the mainsurface of the semiconductor substrate, which comprises:

[0032] forming a trench, wherein a trench-gate will be formed, on themain surface of the semiconductor substrate,

[0033] forming a gate insulating film in the trench,

[0034] forming a polycrystalline silicon film, which will be aconductive film for the trench gate, all over the main surface of thesemiconductor substrate,

[0035] removing the polycrystalline silicon film by using etching andmulti-stage oxidation in combination, thereby forming, in the trench, atrench gate having a substantially flat or concave upper surface,

[0036] forming an insulating film over the main surface of thesemiconductor substrate by thermal oxidation so that the film on thetrench gate becomes thicker than that on the main surface of thesemiconductor substrate by making use of accelerated oxidationphenomenon,

[0037] removing the insulating film by etching and while leaving thethickly formed insulating film on the trench gate, exposing the mainsurface of the semiconductor substrate,

[0038] selectively removing the semiconductor substrate relative to theinsulating film by etching, thereby forming the upper surface of thetrench gate covered with the insulating film equal to or higher than themain surface of the semiconductor substrate, and

[0039] subsequent to the selective etching, introducing impurities fromthe main surface of the semiconductor substrate, thereby forming achannel forming region and a source region.

[0040] Described is a fabrication method of a semiconductor deviceequipped with an FET of a trench-gate structure having a conductivelayer, which will be a gate, disposed in a trench extended in the mainsurface of the semiconductor substrate, which comprises:

[0041] disposing a field relaxing portion at the terminal portion of thetrench gate, forming a trench, wherein a trench-gate will be formed, onthe main surface of the semiconductor substrate;

[0042] forming a gate insulating film in the trench,

[0043] forming a trench gate in the trench,

[0044] forming an insulating film over the main surface of thesemiconductor substrate by thermal oxidation so that the film on thetrench gate becomes thicker than that on the main surface of thesemiconductor substrate by making use of accelerated oxidationphenomenon,

[0045] removing the insulating film by etching and while leaving thethickly formed insulating film on the trench gate, exposing the mainsurface of the semiconductor substrate,

[0046] selectively removing the semiconductor substrate relative to theinsulating film by etching, thereby forming the upper surface of thetrench gate covered with the insulating film equal to or higher than themain surface of the semiconductor substrate, and

[0047] subsequent to the selective etching, introducing impurities fromthe main surface of the semiconductor substrate, thereby forming achannel forming region and a source region.

[0048] Also provided is a fabrication method of a semiconductor device,which comprises:

[0049] forming a trench, wherein a trench-gate will be formed, on themain surface of the semiconductor substrate;

[0050] forming a gate insulating film in the trench,

[0051] forming a trench gate in the trench,

[0052] forming an insulating film over the main surface of thesemiconductor substrate by thermal oxidation so that the film on thetrench gate becomes thicker than that on the main surface of thesemiconductor substrate by making use of the accelerated oxidationphenomenon,

[0053] forming a mask film over the insulating film on the trench gate,

[0054] removing the insulating film by isotropic etching by using themask film and while leaving the insulating film formed thickly on thetrench gate, exposing the main surface of the semiconductor substrate,and

[0055] selectively removing the semiconductor substrate relative to theinsulating film by etching, thereby forming the upper surface of thetrench gate covered with the insulating film equal to or higher than themain surface of the semiconductor substrate.

[0056] Also provided is a fabrication method of a semiconductor device,which comprises:

[0057] (1) forming a semiconductor layer containing first conductivitytype impurities over the main surface of a semiconductor body containingfirst conductivity type impurities,

[0058] (2) forming a field insulating film in a selected region on themain surface of the semiconductor layer,

[0059] (3) forming a trench in the semiconductor layer,

[0060] (4) forming a gate insulating film over the surface inside of thetrench,

[0061] (5) embedding a gate layer inside of the trench wherein the gateinsulating film has been formed,

[0062] (6) etching the main surface of the semiconductor layer so thatthe main surface of the semiconductor layer becomes lower than the endportion of the gate layer contiguous to the gate insulating film,

[0063] (7) introducing second conductivity type impurities in thesemiconductor layer, thereby forming, in the semiconductor layer, afirst semiconductor region which is positioned shallower than the bottomof the trench and at the same time, is in contact with the gateinsulating film, and

[0064] (8) introducing first conductivity type impurities in the firstsemiconductor region, thereby forming, in the first semiconductorregion, a second semiconductor region which is positioned shallower thanthe first semiconductor region and at the same time, is contact with thegate insulating film.

[0065] Also provided is a method for fabricating a semiconductorintegrated circuit device, which comprises:

[0066] etching both an insulating film formed over the main surface of asemiconductor substrate and the semiconductor substrate, thereby forminga connecting hole reaching the inside of the semiconductor substrate,

[0067] causing selective retreat of the insulating film relative to thesemiconductor substrate, thereby widening the connecting hole so as toexpose the main surface of the semiconductor substrate, and

[0068] forming a conductive film in the connecting hole.

[0069] Also provided is a semiconductor integrated circuit device,wherein a connecting hole is formed in an insulating film formed overthe main surface of a semiconductor substrate so as to reach thesemiconductor substrate,

[0070] the connecting hole has an exposing portion of the main surfaceof the semiconductor substrate and a portion reaching the semiconductorsubstrate,

[0071] a conductive film is formed in the connecting hole, and

[0072] the conductive film is electrically connected with thesemiconductor substrate both at the exposing portion of the main surfaceof the semiconductor substrate and the portion reaching thesemiconductor substrate.

[0073] By the above-described means, the upper surface of thetrench-gate conductive layer is formed equal to or higher than the mainsurface of the semiconductor substrate, making it possible to prevent asource offset.

BRIEF DESCRIPTION OF THE DRAWINGS

[0074]FIG. 1 is a plan view illustrating a semiconductor deviceaccording to Embodiment 1 of the present invention;

[0075]FIG. 2 is a fragmentary plan view illustrating the semiconductordevice according to Embodiment 1 of the present invention;

[0076]FIG. 3 is a partial longitudinal cross-sectional view taken alonga line a-a of FIG. 2;

[0077]FIG. 4 is a longitudinal fragmentary cross-sectional viewillustrating, in the order of steps, the semiconductor device accordingto Embodiment 1 of the present invention;

[0078]FIG. 5 is a longitudinal fragmentary cross-sectional viewillustrating, in the order of steps, the semiconductor device accordingto Embodiment 1 of the present invention;

[0079]FIG. 6 is a longitudinal fragmentary cross-sectional viewillustrating, in the order of steps, the semiconductor device accordingto Embodiment 1 of the present invention;

[0080]FIG. 7 is a longitudinal fragmentary cross-sectional viewillustrating, in the order of steps, the semiconductor device accordingto Embodiment 1 of the present invention;

[0081]FIG. 8 is a longitudinal fragmentary cross-sectional viewillustrating, in the order of steps, the semiconductor device accordingto Embodiment 1 of the present invention;

[0082]FIG. 9 is a longitudinal fragmentary cross-sectional viewillustrating, in the order of steps, the semiconductor device accordingto Embodiment 1 of the present invention;

[0083]FIG. 10 is a longitudinal fragmentary cross-sectional viewillustrating, in the order of steps, the semiconductor device accordingto Embodiment 1 of the present invention;

[0084]FIG. 11 is a longitudinal fragmentary cross-sectional viewillustrating, in the order of steps, the semiconductor device accordingto Embodiment 1 of the present invention;

[0085]FIG. 12 is a longitudinal fragmentary cross-sectional viewillustrating, in the order of steps, the semiconductor device accordingto Embodiment 1 of the present invention;

[0086]FIG. 13 is a longitudinal fragmentary cross-sectional viewillustrating, in the order of steps, the semiconductor device accordingto Embodiment 1 of the present invention;

[0087]FIG. 14 is a partially-enlarged fragmentary cross-sectional viewillustrating, in the order of steps, the semiconductor device accordingto Embodiment 1 of the present invention;

[0088]FIG. 15 is a partially-enlarged fragmentary cross-sectional viewillustrating, in the order of steps, the semiconductor device accordingto Embodiment 1 of the present invention;

[0089]FIG. 16 is a partially-enlarged fragmentary cross-sectional viewillustrating, in the order of steps, the semiconductor device accordingto Embodiment 1 of the present invention;

[0090]FIG. 17 is a partially enlarged fragmentary cross-sectional viewillustrating, in the order of steps, the semiconductor device accordingto Embodiment 1 of the present invention;

[0091]FIG. 18 is a partially-enlarged fragmentary cross-sectional viewillustrating, in the order of steps, the semiconductor device accordingto Embodiment 1 of the present invention;

[0092]FIG. 19 is a partially-enlarged fragmentary cross-sectional viewillustrating, in the order of steps, the semiconductor device accordingto Embodiment 1 of the present invention;

[0093]FIG. 20 is a partially-enlarged fragmentary cross-sectional viewillustrating, in the order of steps, the semiconductor device accordingto Embodiment 1 of the present invention;

[0094]FIG. 21 is a partially-enlarged fragmentary cross-sectional viewillustrating, in the order of steps, the semiconductor device accordingto Embodiment 1 of the present invention;

[0095]FIG. 22 is a partially-enlarged fragmentary cross-sectional viewillustrating, in the order of steps, the semiconductor device accordingto Embodiment 1 of the present invention;

[0096]FIG. 23 is a partially-enlarged fragmentary cross-sectional viewillustrating, in the order of steps, the semiconductor device accordingto Embodiment 1 of the present invention;

[0097]FIG. 24 is a partially-enlarged fragmentary cross-sectional viewillustrating, in the order of steps, the semiconductor device accordingto Embodiment 1 of the present invention;

[0098]FIG. 25 is a partially-enlarged fragmentary cross-sectional viewillustrating, in the order of steps, the semiconductor device accordingto Embodiment 1 of the present invention;

[0099]FIG. 26 is a partially-enlarged fragmentary cross-sectional viewillustrating, in the order of steps, the semiconductor device accordingto Embodiment 1 of the present invention;

[0100]FIG. 27 is an equivalent circuit view of MISFET having aprotective diode disposed thereon according to Embodiment 1 of thepresent invention;

[0101]FIG. 28 is a partially-enlarged fragmentary cross-sectional viewillustrating, in the order of steps, the semiconductor device accordingto another embodiment of the present invention; and

[0102]FIG. 29 is a partially-enlarged fragmentary cross-sectional viewillustrating, in the order of steps, the semiconductor device accordingto the another embodiment 1 of the present invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0103] The embodiments of the present invention will hereinafter bedescribed. In all the drawings for describing the embodiments, likemembers of a function will be identified by like reference numerals andoverlapping descriptions will be omitted.

[0104] (Embodiment 1)

[0105]FIG. 1 is a plan view illustrating a power MISFET having atrench-gate structure, which will be the semiconductor device accordingto Embodiment 1 of the present invention, FIG. 2 is a fragmentary planview illustrating the portion a of FIG. 1 in an enlarged scale and FIG.3 is a longitudinal cross-sectional view taken along a line a-a of FIG.2.

[0106] The MISFET of this embodiment is formed on a semiconductorsubstrate obtained, for example, by forming an epitaxial layer 2 on ann⁺-type semiconductor body 1, for example, made of single crystalsilicon by the epitaxial growth technique. This MISFET is disposed inthe form of a rectangular ring along the outer periphery of thesemiconductor substrate and it is formed within a region surrounded by afield insulating film 3 (shown by a double slash in FIG. 2) having arectangular portion inside of the corner. Within the above-describedregion, a plurality of hexagonal or flat pentagonal cells (semiconductorisland region) having a trench-gate structure are disposed regularly anda mesh-gate structure wherein gates are two-dimensionally disposed inthe lattice form and cells are connected in parallel each other isformed. The trench-gate structure is thus formed to separate the mainsurface of the semiconductor substrate into semiconductor island regionsfor cells.

[0107] In each cell, that is, in each semiconductor island region, ann⁻-type first semiconductor layer 2 a formed over the semiconductor body1 serves as a drain region, a p-type second semiconductor layer 2 bformed over the first semiconductor layer 2 a serves as a base regionwherein a channel is to be formed, and an n⁺-type third semiconductorlayer 2 c formed over the second semiconductor layer 2 b serves as asource region, thus forming a vertical FET.

[0108] A trench gate (gate electrode) 4 is formed, via a gate insulatingfilm 5, in a trench which extends from the main surface of thesemiconductor substrate to the n⁻-type second semiconductor layer 2 awhich will be a drain region. As the trench gate 4, for exampleimpurity-introduced polycrystalline silicon is employed, while the gateinsulating film 5 is made of a multilayer film obtained, for example, bysuccessively stacking a thermal oxide film of about 27 nm thick and adeposition film of about 50 nm thick.

[0109] As illustrated in FIGS. 19 to 21 which will be described later,the upper surface 4 a of the trench gate 4 of this embodiment is formedhigher than the surface of the third semiconductor layer 2 c, which willbe a source region, that is, the main surface of the semiconductorsubstrate. Such a constitution makes it possible to prevent the trenchgate 4 from getting out of the source region, that is, preventoccurrence of a source offset even if the source region is made shallow.The trench gate 4 is desired to have a substantially flat or convexupper surface.

[0110] The trench gates 4 of adjacent cells are connected each other,thus forming a mesh-gate structure wherein they are disposedtwo-dimensionally in the form of a lattice. The trench gate 4 of each ofthe cells positioned at the outer periphery is connected, for example,with a polycrystalline-silicon-made gate wiring 6 in the vicinity at theouter periphery of a semiconductor chip.

[0111] The gate wiring 6 is electrically connected with a gate guardring 8 (partially shown by a broken line in FIG. 2) which is formedthereover through an interlayer insulating film 7 and is, for example,made of silicon-containing aluminum. The gate guard ring 8 is integratedwith a rectangular gate electrode 9 (partially shown by a broken line inFIG. 2) which is disposed at the rectangular portion of the fieldinsulating film 3. The gate electrode 9 has a connecting region (shownby a broken line in FIG. 1) with the gate 4.

[0112] A third semiconductor layer 2 c, which will be a source, iselectrically connected with a source wiring 10 (partially shown by abroken line in FIG. 2) which is formed over the main surface of thesemiconductor substrate through the interlayer insulating film 7 and is,for example, made of silicon-containing aluminum. The source wiring 10has a connecting region (shown by a broken line in FIG. 1) with thethird semiconductor layer 2 c, which will be a source. This sourcewiring 10 is electrically connected with not only third semiconductorlayer 2 c which will be a source but also a p⁺-type contact layer 11disposed in the second semiconductor layer 2 b to make the basepotential, that is, the potential of a channel forming region constant.

[0113] As is illustrated in FIG. 3 or 22, a protective diode 12 having aback-to-back structure is disposed between the gate and source. In theprotective diode 12, the n⁺-type semiconductor regions 12 a and p-typesemiconductor regions 12 b are alternately formed in the form of aconcentric ring, and with the n⁺-type semiconductor regions 12 at bothends are electrically connected the gate electrode 9 and source wiring10, respectively. A shown in the circuit diagram of FIG. 27, theprotective diode is disposed between the gate and the source forprotecting breakdown of the gate insulating film from the surge from thesource.

[0114] At the outer periphery of the field insulating film 3, disposedis a source guard ring 13 obtained by connecting an n⁺-typesemiconductor region 13 a disposed over the main surface of thesemiconductor substrate with a wiring 13 b (partially shown by a brokenline in FIG. 2), for example, made of silicon-containing aluminum.Similar to the source wiring 10, the wiring 13 b of the source guardring 13 is connected with the n⁺-type semiconductor region 12 a of theprotective diode 12.

[0115] The gate wiring 6 and gate guard ring 8 are disposed over thefield insulating film 3 disposed in the form of a rectangular ring,while the gate electrode 9 and protective diode 12 are disposed over therectangular portion disposed at the corner of the field insulating film3.

[0116] Along the field insulating film 3 in the rectangular ring form, ap-type well 14 is formed therebelow. By connecting the p-type well 14with the terminal portion of the trench gate 4 through the gateinsulating film 5, a depletion layer can be gently extended below thefield insulating film 3 and discontinuity of the depletion layer can beprevented. The p-type well 14 therefore functions as a field relaxingportion for relaxing the electric field at the terminal portion of thetrench gate 4.

[0117] All over the main surface of the semiconductor substrate, aprotective insulating film 15 is formed, for example, by stackingpolyimide on a silicon oxide film, which has been obtained by plasma CVDusing as a main source gas tetraethoxysilane (TEOS), to cover the gateguard ring 8, gate electrode 9, source wiring 10 and source guard ring13. A contact hole is made in this protective insulating film 15 topartially expose the gate electrode 9 and source wiring 10. The gateelectrode 9 and source wiring 10 to be exposed by this contact hole willbecome connecting regions with the gate and source, respectively.Electric connection to each of these connecting regions is conducted bywire bonding or the like.

[0118] As the connecting region with the drain, a drain electrode 16which is electrically conductive with the n⁺-type semiconductorsubstrate 1 is formed, for example, as a nickel-titanium-nickel-silverlaminated film all over the reverse side of the semiconductor substrate,and the drain electrode 16 is electrically connected with a lead frameby a conductive adhesive.

[0119] A fabrication method of the above-described semiconductor devicewill next be described based on FIGS. 4 to 26.

[0120] Over the n⁺ semiconductor body 1, for example, made of singlecrystal silicon having arsenic (As) introduced therein, an n⁻ typeepitaxial layer 2 having a lower concentration than the semiconductorbody 1 is formed to give a thickness of about 5 μm by epitaxial growth.A silicon oxide film of about 40 nm thick is then formed over the mainsurface of this semiconductor substrate, for example, by thermaloxidation, followed by the formation, as a mask of a silicon nitride(SiN) film over this silicon oxide film in the rectangular ring formalong the outer periphery of the semiconductor substrate. A fieldinsulating film 3 having a rectangular portion inside of the corner isthen formed by thermal oxidation in self alignment with the siliconnitride film. Along the inner periphery of the field insulating film 3,ions, for example, boron (B) are implanted and the impurities thusintroduced are diffused, whereby a p-type well 14 which will be a fieldrelaxing portion is formed as shown in FIG. 4. The impurityconcentration of the p-type well 14 is, for example, set equal to orlower than that of the second semiconductor layer 2 b.

[0121] A silicon oxide film is then formed over the main surface of thesemiconductor substrate. Within a cell forming region surrounded by thefield insulating film 3, the silicon oxide film is patterned to form acontact hole which exposes a portion of the main surface of thesemiconductor substrate over which a trench gate (gate electrode) of amesh-gate structure wherein gates are two-dimensionally arranged in thelattice form is formed. With this silicon oxide film as a mask, a trenchof, for example, about 1.6 μm thick is formed in the main surface of thesemiconductor substrate by dry etching. This trench separates the mainsurface of the semiconductor substrate into plural semiconductor islandregions 2 on which a cell is to be formed.

[0122] The trench formation is completed, for example, by making atrench by dry etching, removing the silicon oxide film, which will be amask, by wet etching and then chemical dry etching to remove the angularportion at the bottom edge. A gate insulating film 5 is then formed bystacking a silicon oxide film of about 50 nm thick over a thermal oxidefilm of about 27 nm thick by CVD (Chemical Vapor Deposition) asillustrated in FIGS. 5 and 15.

[0123] All over the main surface of the semiconductor substrateincluding the inside of the trench, a polycrystalline silicon film 4′which will be a conductive film of the trench gate, is formed by CVD.Into this polycrystalline silicon film 4′, impurities (ex. phosphorus)for reducing its resistance are introduced during or after deposition.The impurity concentration is set to fall within a range of from1E18/cm³ to 1E21/cm³ (1×10¹⁸ to 1×10²¹/cm³), which is higher than thethat of the n⁻-type epitaxial layer 2 (main surface of the semiconductorsubstrate). Owing to such a high impurity concentration, acceleratedoxidizing phenomenon which will be described later can be usedeffectively. This stage is illustrated in FIG. 6.

[0124] After the polycrystalline silicon film 4′ is etched back bymultistage oxidation wherein oxidation and etching are repeated severaltimes and is thereby flattened, it is removed by etching, whereby atrench gate 4 is formed in the trench. Simultaneously with this etching,a gate wiring 6 connected with the trench gate 4 and a polycrystallinesilicon film 9 a which will lie below the gate electrode 9 are formedover the rectangular ring portion of the field insulating film 3, whichare illustrated in FIGS. 7 and 16.

[0125] The flattening upon formation of the trench gate 4 prevents theformation of a concave portion on the upper surface of the trench gate4. If the concave portion is formed, formation of an insulating film inthe subsequent step is not sufficient on this concave portion and at thesame time, the progress of etching is accelerated, which happens toexpose the trench gate 4. The above-described flattening prevents suchexposure of the trench gate 4. Flattening can alternatively be conductedby CMP (Chemical Mechanical Polishing).

[0126] The unnecessary portion of the silicon oxide film remaining onthe main surface of the semiconductor substrate is then removed. Afterexposure of the main surface of the semiconductor substrate, aninsulating film 17 made of, for example, a silicon oxide film, is formedby thermal oxidation all over the main surface of the semiconductorsubstrate and trench gate 4. Since the impurity concentration of thepolycrystalline silicon film which constitutes the trench gate 4 ishigher than that of the main surface of the semiconductor substrate, theinsulating film 17 is formed, by the accelerated oxidation phenomenon,to be thicker on the trench gate 4 (thickness: L1) than on the mainsurface of the semiconductor substrate (thickness: L2). Upon formationof the insulating film 17 having a greater film thickness (L1) over thetrench gate 4 by accelerated oxidation, the insulating film 17 is formedover the main surface of the low-concentration epitaxial layer 2 so thatthe film thickness (L1) of the insulating film over the trench gate 4can be made greater than that (L2) over the main surface of theepitaxial layer 2. This stage is illustrated in FIGS. 8 and 17.

[0127] The insulating film 17 is then removed by dry etching and themain surface of the semiconductor substrate is exposed with thethickly-formed insulating film 17 being left on the trench gate 4, asillustrated in FIGS. 9 and 18.

[0128] Dry etching is then conducted using a CF₄ gas to selectivelyremove silicon, relative to silicon oxide, from the main surface of thesemiconductor substrate, whereby the main surface 2 a of thesemiconductor substrate is made lower than the upper surface 4 a of thetrench gate 4. In other words, the upper surface 4 a of the trench gate4 covered with silicon oxide is formed equal to or higher than thesurface of the third semiconductor layer 2 c, which will be a sourceregion, that is, the main surface of the semiconductor substrate, asillustrated in FIGS. 10 and 19. By oxidation, the etching damage isremoved and an oxide film 17 a for reinforcing the gate insulating film5 and insulating film 17 are formed as illustrated in FIG. 20.

[0129] After formation of an insulating film 12 c made of silicon oxide,a polycrystalline silicon film is deposited over the insulating film 12c. Then, p-type impurities are introduced into the polycrystallinesilicon film, followed by patterning, on the rectangular portion of thefield insulating film 3, into a concentric ring form surrounding thepolycrystalline silicon film 9 a on the gate electrode 9. Uponpatterning, the insulating film 12 c serves as an etching stopper forpreventing the trench gate 4 and gate wiring 6 from being patterned.Then, an n⁺-type semiconductor region 12 a is formed, for example, byion implantation, whereby a protective diode 12 having the n⁺-typesemiconductor region 12 a and p-type semiconductor region 12 b formedalternately in the concentric ring form is formed as illustrated inFIGS. 11 and 22.

[0130] Ions such as p-type impurities (ex. boron) are then implanted allover the surface of the epitaxial layer 2, followed by diffusiontreatment for about 100 minutes in a 1% O₂-containing nitrogen gasatmosphere at about 1100° C., whereby a p-type second semiconductorlayer 2 b, which will be a channel forming region, is formed. Then, ionssuch as n-type impurities (ex. arsenic) are selectively implanted,followed by annealing treatment for about 30 minutes in a 1%O₂-containing nitrogen gas atmosphere at about 950° C., whereby a thirdsemiconductor layer 2 c, which will be a source region, is formed. Thedeeper portion of the epitaxial layer 2 into which impurities have notbeen introduced, more specifically, a portion of the epitaxial layer 2lying between the second semiconductor layer 2 b and semiconductor body1 becomes the first semiconductor layer 2 a serving as a drain region.The number of the steps may be reduced by simultaneously conducting ionimplantation of the n⁺-type semiconductor region 12 a and the firstsemiconductor layer 2 a. This stage is illustrated in FIGS. 12 and 21.

[0131] Since the second semiconductor layer 2 b, which will be a channelforming region, and the third semiconductor layer 2 c, which will be asource region, are formed by ion implantation after the main surface 2 dof the semiconductor substrate is lowered relative to the upper surface4 a of the trench gate 4 by causing the semiconductor substrate toretreat, the profile in the depth direction in the semiconductorsubstrate 2 and the depth of each of the second semiconductor layer 2 band third semiconductor layer 2 c can be controlled precisely, whichmakes it possible to accelerate thinning of the second semiconductorlayer 2 b and third semiconductor layer 2 c. In short, the depth of thesecond semiconductor layer 2 b can be controlled precisely, making itpossible to control the channel length precisely.

[0132] All over the main surface of the semiconductor substrate, aninterlayer insulating film 7 is formed by depositing, for example, BPSGto give a film thickness of about 500 nm.

[0133] By anisotropic dry etching using a CHF₃ gas, a contact hole CH(contact hole) is made in the interlayer insulating film 7 to exposeeach of the third semiconductor layer 2 c which will be a source region,gate wiring 6, source guard ring semiconductor region 13 a and aconnecting region with the protective diode. All over the main surfaceof the semiconductor substrate including the inside of each of thecontact holes, a conductive film (metal film) made of, for example,silicon-containing aluminum is formed. By patterning of the metal film,the gate guard ring 8, gate electrode 9, source wiring 10 and sourceguard ring 13 are formed, as illustrated in FIG. 12.

[0134] Conventionally, a contact layer 11 has been formed to extend fromthe main surface of the semiconductor substrate to the secondsemiconductor layer 2 b, and with this contact layer 11 and the thirdsemiconductor layer 2 c around the contact layer 11, the source wiring10 has been connected. In this embodiment, on the other hand, a contacthole CH is formed to extend to the second semiconductor layer 2 b byetching as illustrated in FIG. 23, followed by direct introduction ofp-type impurities such as boron into the second semiconductor layer 2 bexposed by the contact hole CH as illustrated in FIG. 24. The p-typecontact layer 11 is formed deeply by such a constitution, leading to areduction in the generation amount of avalanche. Upon formation of thesource, a mask for covering the contact layer 11 becomes unnecessary sothat a subsequent photoresist step can be omitted. If the contact layer11 is not required at the contact portion of another contact hole CHowing to the fabrication of the device into IC, it is possible to form acontact layer 11 only for a contact hole CH to be electrically connectedeasily with the source wiring 10 by using another mask covering thecontact.

[0135] In this Embodiment, as illustrated in FIG. 25, after introductionof impurities from the contact hole CH, silicon oxide is removed fromthe interlayer insulating film 7 by selective etching relative tosilicon in the main surface of the semiconductor substrate, whereby thesurface of the third semiconductor layer 2 c is exposed in selfalignment with the contact hole CH. As illustrated in FIG. 26, such aconstitution makes it possible to enlarge the contact area between thethird semiconductor layer 2 c and source wiring 10, thereby reducing theconnection resistance.

[0136] In the next place, a protective insulating film 15 which coverstherewith the whole main surface of the semiconductor substrate isformed by applying and stacking polyimide onto a silicon oxide filmformed by plasma CVD using tetraethoxysilane (TEOS) gas as a main sourcegas. In the resulting protective insulating film 15, a contact hole toexpose the connecting region of each of the gate electrode 9 and thesource wiring 10 is formed, followed by polishing treatment on thereverse side of the n⁺-type semiconductor body 1. A drain electrode 14is then formed, for example, by successively depositing and stackingnickel, titanium, nickel and silver on the reverse side as illustratedin FIG. 3.

[0137] In this Embodiment, the p-type well 14 is disposed as a fieldrelaxing portion in the form of a rectangular ring. Alternatively, it ispossible to make a contact hole in the field insulating film 3 andintroducing impurities from this contact hole to have the p-type wells14 studded below the field insulating film in the ring form. In thisconstitution, the field relaxing portion can be formed after theformation of the gate wiring 6.

[0138] (Embodiment 2)

[0139] In FIGS. 28 and 29, another embodiment of the present inventionis illustrated.

[0140] This embodiment differs from the above-described one in the stepfor lowering the main surface 2 d of the semiconductor substraterelative to the upper surface 4 a of the trench gate 4. This embodimentis substantially similar to the above-described one in the other stepsso a description of the other steps is omitted.

[0141] The fabricating method of the semiconductor device according tothis embodiment will next be described based on FIGS. 28 and 29.

[0142] After the step of the above-described embodiment as illustratedin FIG. 18, a photoresist film 30 is for example formed, as illustratedin FIG. 28, over the insulating film 17 overlying the trench gate 4.

[0143] With the photoresist film 30 as a mask, the semiconductorsubstrate 2 is subjected to isotropic etching to selectively etch thesemiconductor substrate 2 relative to the insulating films 5,17, wherebythe main surface 2 d of the semiconductor substrate is made lower thanthe upper surface 4 a of the trench gate 4 as illustrated in FIG. 29.

[0144] The weak insulating film 17 formed by accelerated oxidation isthus protected by causing the surface of the semiconductor substrate toretreat with the photoresist film 30 over the insulating film 17 as amask, which makes it possible to prevent the invasion of an Si etchinggas into the trench gate 4 and, in turn, etching of the trench gate 4.

[0145] After the removal of the photoresist film 30, steps on and afterthe formation of an insulating film 17 a, that is, the steps on andafter FIG. 20, are conducted in a similar manner to the above-describedembodiment, whereby a semiconductor device is formed.

[0146] According to this embodiment, it becomes possible to protect theweak insulating film 17 and prevent the trench gate 4 from being etchedduring etching of the semiconductor substrate 2 for causing the surfaceof the semiconductor substrate to retreat, leading to an improvement inthe reliability of a semiconductor device.

[0147] The inventions made by present inventors have so far beendescribed specifically based on the above-described embodiments. Itshould however be borne in mind that the present invention is notlimited by them, but can be modified within an extent not departing fromthe scope of the present invention.

[0148] The present invention can be adapted, for example, to IGBT(Integrated Gate Bipolar Transistor), as well as power MISFET.

[0149] Advantages of the representative inventions, among the inventionsdisclosed by the present application, will next be described briefly.

[0150] (1) The present invention is effective for preventing a sourceoffset by forming the upper surface of the trench-gate conductive layerequal to or higher than the main surface of the semiconductor substrate.

[0151] (2) In the present invention, the above-described advantage (1)makes it possible to promote thinning of a source.

[0152] (3) In the present invention, the above-described advantage (2)makes it possible to promote miniaturization of a cell.

What is claimed is:
 1. A metal insulator semiconductor field effect typesemiconductor device, comprising: a semiconductor substrate having firstand second main surfaces which are opposite to each other; a trenchformed in said semiconductor substrate to give a predetermined depthfrom the first main surface, said trench separating said first mainsurface of said semiconductor substrate into semiconductor islandregions for forming metal insulator semiconductor field effect typecells, respectively; a source region, a channel forming region and adrain region formed in the order of mention in the depth direction ofthe semiconductor island region from said first main surface of eachsaid semiconductor island region; a gate insulating film formed over theinside surface of said trench; and a gate electrode formed over saidgate insulating film so as to embed said trench with said gateelectrode, said gate electrode extending vertically from said trenchtoward a position higher than said first main surface of saidsemiconductor island region.
 2. A metal insulator semiconductor fieldeffect type semiconductor device, comprising: a semiconductor substratehaving first and second main surfaces which are opposite to each other;a trench formed in said semiconductor substrate to give a predetermineddepth from the first main surface, said trench separating said firstmain surface of said semiconductor substrate into semiconductor islandregions for forming metal insulator semiconductor field effect typecells, respectively; a source region, a channel forming region and adrain region formed in the order of mention in the depth direction ofsaid semiconductor island region from said first main surface of eachsaid semiconductor island region; a gate insulating film formed over theinside surface of said trench; and a gate electrode formed over saidgate insulating film so as to embed said trench with said gateelectrode, said gate electrode having a protrusion extending verticallyfrom said trench toward a position higher than said first main surfaceof said semiconductor island region.
 3. A metal insulator semiconductorfield effect type semiconductor device according to claim 2, furthercomprising: a peripheral semiconductor region having the sameconductivity type as that of said channel forming region formed inanother portion of said first main surface of said semiconductorsubstrate; and a conductive layer formed over said peripheralsemiconductor region via an insulating film and electrically connectedwith said gate electrode.
 4. A method of fabricating a trench-gate typesemiconductor device, comprising the steps of: making a trench in themain surface of a semiconductor substrate; forming a gate insulatingfilm on the inside surface of said trench; forming a gate electrode toembed therewith said trench; forming an insulating film over the mainsurface of said semiconductor substrate so that the film thickness onsaid gate electrode becomes greater than that on the main surface ofsaid semiconductor substrate; etching said insulating film to expose themain surface of said semiconductor substrate while leaving saidthickly-formed insulating film on said gate electrode; and selectivelyetching said semiconductor substrate relative to said insulating film soas to form the upper surface of said gate electrode, covered with saidthe insulating film, higher than the main surface of said semiconductorsubstrate.
 5. A method of fabricating a trench-gate type semiconductordevice, comprising the steps of: making a trench in the main surface ofa semiconductor substrate; forming a gate insulating film on the insidesurface of said trench; forming a gate electrode to embed therewith saidtrench; forming an insulating film over the main surface of saidsemiconductor substrate so that the film thickness on said gateelectrode becomes greater than that on the main surface of saidsemiconductor substrate; etching said insulating film to expose the mainsurface of said semiconductor substrate while leaving saidthickly-formed insulating film on said gate electrode; selectivelyetching said semiconductor substrate relative to said insulating film toform the upper surface of said gate electrode, covered with saidinsulating film, higher than the main surface of said semiconductorsubstrate; and introducing, after selective etching, respectiveimpurities from the main surface of said semiconductor substrate to forma channel forming region and a source region.
 6. A method of fabricatinga trench-gate type semiconductor device, comprising the steps of: makinga trench in the main surface of a semiconductor substrate; forming agate insulating film on the inside surface of said trench; forming apolycrystalline silicon film to cover all over the main surface of saidsemiconductor substrate and embed therewith said trench; oxidizing andetching said polycrystalline silicon film to form, in said trench, agate electrode protruded from the main surface of said semiconductorsubstrate; forming an insulating film over the main surface of saidsemiconductor substrate so that the film thickness on the gate electrodebecomes greater than that on the main surface of said semiconductorsubstrate; etching said insulating film to expose the main surface ofsaid semiconductor substrate while leaving said thickly-formedinsulating film on said gate electrode; selectively etching saidsemiconductor substrate relative to said insulating film to form theupper surface of said gate electrode, covered with said insulating film,higher than the main surface of said semiconductor substrate; andintroducing, after selective etching, respective impurities from themain surface of said semiconductor substrate to form a channel formingregion and a source region.
 7. A method of fabricating a trench-gatetype semiconductor device, comprising the steps of: forming a fieldrelaxing region of a first conductivity type in the peripheral portionof the main surface of a semiconductor substrate wherein a trench gateis to be formed; forming, in the main surface of said semiconductorsubstrate, a trench wherein the trench gate is to be formed; forming agate insulating film in said trench; forming a gate electrode in saidtrench; forming an insulating film over the main surface of saidsemiconductor substrate so that the film thickness on said gateelectrode becomes greater than that on the main surface of saidsemiconductor substrate; removing said insulating film by etching toexpose the main surface of said semiconductor substrate while leavingsaid thickly-formed insulating film on said gate electrode; selectivelyremoving said semiconductor substrate relative to said insulating filmby etching to form the upper surface of said gate electrode, coveredwith the insulating film, higher than the main surface of saidsemiconductor substrate; and introducing, after selective etching,respective impurities from the main surface of said semiconductorsubstrate to form a channel forming region of a first conductivity typeand a source region of a second conductivity type.
 8. A method offabricating a trench-gate type semiconductor device, comprising thesteps of: making a trench in the main surface of a semiconductorsubstrate; forming a gate insulating film in said trench; forming a gateelectrode in said trench; forming an insulating film over the mainsurface of said semiconductor substrate so that the film thickness onsaid gate electrode becomes greater than that on the main surface ofsaid semiconductor substrate; forming a mask film over said insulatingfilm on said gate electrode; removing said insulating film by isotropicetching by using said mask film to expose the main surface of saidsemiconductor substrate while leaving said thickly-formed insulatingfilm on said gate electrode; and selectively removing said semiconductorsubstrate relative to said insulating film by etching to form the uppersurface of said gate electrode, covered with the insulating film, higherthan the main surface of said semiconductor substrate.
 9. A methodaccording to any one of claims 4 to 8, wherein the impurityconcentration of said gate electrode is set higher than that in the mainsurface of said semiconductor substrate.
 10. A fabricating method of atrench-gate type semiconductor device, comprising the steps of: (1)forming, over the main surface of a semiconductor body containingimpurities of a first conductivity type, a semiconductor layercontaining impurities of the first conductivity type; (2) forming afield insulating film in a selected region of the main surface of saidsemiconductor layer; (3) making a trench in said semiconductor layer;(4) forming a gate insulating film on the inside surface of said trench;(5) embedding a gate conductive layer in said trench having said gateinsulating film formed therein; (6) etching the main surface of saidsemiconductor layer so that the main surface of said semiconductor layerbecomes lower than the end portion of said gate conductive layercontiguous to said gate insulating film; (7) introducing impurities of asecond conductivity type in said semiconductor layer to form therein afirst semiconductor region which is shallower than the bottom portion ofsaid trench and is contiguous to said gate insulating film; and (8)introducing impurities of the first conductivity type in said firstsemiconductor region to form therein a second semiconductor region whichis shallower than said first semiconductor region and is contiguous tosaid gate insulating film.
 11. A fabricating method according to claim10, further comprising, prior to the step (7), forming, over said fieldinsulating film, a polycrystalline silicon layer wherein a protectivediode is to be formed.
 12. A fabricating method according to claim 11,further comprising forming a back-to-back diode in said polycrystallinesilicon layer.
 13. A fabricating method according to claim 10, whereinsaid step (5) comprises: forming a polycrystalline silicon layer on themain surface of said semiconductor layer including said trench; etchingback said polycrystalline silicon layer to leave said polycrystallinesilicon layer inside said trench; and oxidizing the main surface of saidpolycrystalline silicon layer in said trench.
 14. A fabricating methodof a semiconductor integrated circuit device, comprising the steps of:etching an insulating film formed over the main surface of asemiconductor substrate and said semiconductor substrate to form aconnecting hole reaching the inside of said semiconductor substrate;selectively causing said insulating film to retreat relative to saidsemiconductor substrate and expanding said connecting hole to expose themain surface of said semiconductor substrate; and forming a conductivefilm in said connecting hole.
 15. A fabricating method according toclaim 14, further comprising, prior to said step for expanding saidconnecting hole, introducing impurities through said connecting hole toform a high-concentration region in said semiconductor substrate.
 16. Afabricating method according to claim 15, wherein said semiconductorsubstrate has a first semiconductor region of a first conductivity typeand a second semiconductor region of a second conductivity type formedtherebelow, said connecting hole extends to said second semiconductorregion, and said conductive film is electrically connected with saidfirst semiconductor region, in said connecting hole, at the main surfaceand wall surface of said semiconductor substrate.
 17. A fabricatingmethod according to claim 16, further comprising, prior to said step forexpanding said connecting hole, introducing impurities through saidconnecting hole to form, in said second semiconductor region, a thirdsemiconductor region of the second conductivity type having an impurityconcentration higher than that of said second semiconductor region.